(a) Field of the Invention
The present invention relates to a combinational delay circuit for a digital frequency multiplier and, more particularly, to a combinational delay circuit capable of fine adjustment of a delay time.
(b) Description of the Related Art
A digital frequency multiplier is generally used for generating a clock signal having a higher frequency and a clock phase in synchrony with the phase of an input reference clock signal. Such a digital frequency multiplier is described, for example, by T. Shimizu in xe2x80x9cA Multimedia 32b RISC Microprocessor with 16 Mb DRAMxe2x80x9d, ISSCC Digest of Technical Papers, 1996 IEEE International Solid-state Circuit Conference, pp.216 to 217, Feb. 1996. Patent Publications U.S. Pat. Nos. 5,422,835 and 5,530,837 also describe related devices.
FIG. 1 shows a conventional combinational delay circuit in a frequency multiplier capable of quadruple-multiplying the clock frequency of a reference clock signal. Four delay sets each including an individual delay circuit 101, 102, 103 or 104 and a selector 105, 106, 107 or 108 are serially cascaded from one another for receiving a reference (first) clock signal 111 to generate second through fifth clock signals 112 to 115. In each delay set, the delay time of the delay circuit 101, 102, 103 or 104 is controlled by a corresponding one of the selectors 105, 106, 107 and 108 to have a plurality of unit delay times (td), wherein td is a unit delay time effected by each of the delay segments having an equal configuration.
A phase comparator 109 compares the fifth clock signal 115 against the reference clock signal 111 to supply either UP-signal 116 or DOWN-signal 117 to an UP/DOWN (U/D) counter 110 depending on the phase of the fifth clock signal 115 relative to the phase of the reference clock signal 111. The U/D counter 110 supplies a control signal 118 for controlling the selectors 105 to 108 to equalize the phase of the fifth clock signal 115 with that of the reference clock signal 111.
By the above control, since time delays of the respective delay circuits 101 to 104 are controlled by the single control signal 118, the timing difference between each consecutive two of the clock signals 112 to 115 is equal to xc2xc of the clock cycle of the reference clock signal 111. By making a logical sum (OR) of the four clock signals 112 to 115, a quadruple-multiplication of the reference clock signal 111 can be effected to generate a clock signal having a quadruple-multiplied frequency.
Table 1 shows the relationship between the desired total phase delay of the cascaded delay circuits 101 to 104 and the delays actually effected by the respective delay circuits 101 to 104 in the combinational delay circuit of FIG. 1.
Table 2 shows the relationship between the total phase delay and the outputs 112 to 115 of the respective delay circuits 101 to 104, which is obtained from Table 1.
As shown in Tables 1 and 2, the frequency multiplier having the combinational delay circuit described above generates output clock signals having a unit delay which is a quadruple of the unit delay time (td) of each delay circuit. More specifically, the resultant quadruple frequency multiplier cannot adjust the time delay as fine as within four times the unit delay time of each delay circuit, and the error of the clock cycle of the clock signal generated by the frequency multiplier is as high as 3xc3x97td at a maximum.
Specifically, if a total phase delay of 5 unit delays (5xc3x97td) is to be effected, for example, each delay circuit selects 2 delay units (2xc3x97td), whereby the output of the fifth clock signal 115 has a phase delay of 8 unit delays (8xc3x97td) with respect to the reference clock signal 111, which means the presence of an error of 3xc3x97td in the timing of the clock pulse generated by the fifth delay circuit and preceding the clock pulse corresponding to the next pulse in the reference clock signal.
More generally, the error of the phase of the clocks in the output of the frequency multiplier after the logical sum of the respective outputs of the delay circuits resides mostly at specified clocks.
It is therefore an object of the present invention to provide a combinational delay circuit for use in a frequency multiplier, which is capable of outputting a multiplied clock signal having a minimum adjustable delay time substantially equal to the unit delay time of the delay segments of the delay circuits.
It is another object of the present invention to provide a combinational delay circuit, wherein errors of the phase of the clock pulses are substantially uniformly distributed among the clock pulses.
The present invention provides, in one aspect, a combinational delay circuit comprising a first delay circuit having at least one basic delay line including a plurality of cascaded delay segments each effecting a unit time delay, a latch array having a plurality of latch elements each receiving an output from a corresponding one of the delay segments, a plurality of second delay circuits coupled to one another in a cascaded configuration, each of the second delay circuits having a delay element corresponding to said delay line for effecting a time delay substantially equal to the unit time delay, the delay element in each of the second delay circuits receiving an output from a corresponding one of the latch elements by responding to an output from a preceding one of the second delay circuits in terms of the cascaded configuration.
The present invention also provides, in another aspect, a combinational delay circuit for multiplying a frequency of an reference clock signal, comprising a plurality of cascaded delay sets each including a delay circuit having a plurality of cascaded delay segments, each such delay segment effecting a unit time delay; a selector for selecting an output from one of the delay segments as an output of the delay sets, a phase comparator for comparing the phase of an output of a last stage of the cascaded delay circuits against the phase of the reference clock signal, to output a phase difference signal, and a control section for responding to the phase difference signal to control one of the selectors for the selection of one of the delay circuits, the one of the selectors being specified based on a predetermined order of selection depending on the phase difference signal.
In accordance with the combinational delay circuit of the present invention, a frequency multiplier having the combinational delay circuit allows a fine adjustment of the clock delay with respect to the reference clock. In addition, the timing of the clock pulses is controlled so that the error is substantially distributed among the clock pulses.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.